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| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semiconductor inc. all rights reserved. applications ? ethernet pseudo-wires across a packet switch network features ethernet pseudo-wire emulation functions supports the following f unctions for ethernet pseudo- wire emulation over the packet domain: ? transports the complete ethernet frame (less preamble and fcs) across the psn ? supports up to 127 point-to-point pseudo-wire links across the psn ? vlan priority field may be used to determine class of service on the psn ? complies with the standards for ethernet pseudo- wires proposed in the ietf?s pwe3 working group network interfaces ? 3 x 100 mbit/s mii interfaces system interfaces ? flexible 32-bit host cpu interface (motorola powerquicc? ii compatible) ? dual address dma transfer of packets to or from the cpu ? on-chip packet memory for self-contained operation packet processing functions ? flexible, multi-protocol packet encapsulation, with support for ipv4/6, mpls, l2tp, pwe3 ? wire speed processing and forwarding of packets ? packet sequencing and re-ordering where required ? four classes of service with programmable priority mechanisms (wfq and sp) ? flexible classification of incoming packets at layers 2, 3, 4 and 5 october 2004 ordering information zl50130 pbga -40 c to +85 c zl50130 ethernet pseudo-wires across a psn data sheet figure 1 - high level overview packet receive/classifier packet transmit - add layer 2/3 headers task manager memory management / on-chip packet memory host processor interface with dma support protocol engine mac mac optional off-chip packet memory 0-8 mbytes ssram host processor interface motorola powerquicc tm ii compatible packet switched network interface 100 mbit/s mii customer end services 100 mbit/s mii
zl50130 data sheet 2 zarlink semiconductor inc. description the zl50130 is part of a range of highly functional brid ging devices. it provides the capability to extend a local area network based on ethernet across a service provider?s packet switched network. this allows a company with multiple sites to manage its network as though it was a single lan. in conjunction with an ethernet aggr egation network, the zl50130 provides th e dataplane requirements of the inter- working function between the customer end services and the provider?s packet swit ched network (see figure 2). it can support wire-speed processing of up to 100 mbit/s of traffic in each directi on, and provides up to 127 separate pseudo-wire connections across the psn. packets arriving from a single customer end se rvice may all be directed onto a single pseudo-wire, or split across multiple c onnections based on source and des tination addresses. this is useful in the case where the customer is using the ethernet pseudo-wire service to connect multiple sites. on packet egress the device includes four different classes of service, allowing priority treatment of cu stomer traffic, depending on the service level agreement between the customer and provider. the user priority field in the packet?s vlan tag (if any) may be used to determine the appropriate class of service to be used on the psn. packets received from the ethernet interfaces are pa rsed to determine the egress destination, and are appropriately queued to the customer end service, passed up to the host processor, or sent back toward the packet interface. again there are four differ ent classes of service to allow differ entiation between cust omers with different service level agreements, or based on the use of vlan tag priority. the zl50130 includes sufficient on-chip memory to a llow completely self-contained operation, reducing system costs and simplifying the design. for a pplications that do require more memory (e.g., where the network has a very high packet delay variation), the device supports up to 8 mbytes of external synchronous zbt sram. figure 2 - provider edge inter-working function using the zl50130 provider edge interworking function ethernet switch e.g. mvtx2604 mvtx2804 aggregation and adaptation functions phy phy phy phy phy phy phy phy phy customer end services psn bound flow ce bound flow zl50130 ethernet pseudo-wire device packet receive/classifier packet transmit - add layer 2/3 headers task manager memory management / on-chip packet memory host processor interface with dma support protocol engine mac mac packet switch network zl50130 data sheet table of contents 3 zarlink semiconductor inc. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.0 changes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 psn-bound flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 ce-bound flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.3 host packet generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.4 external memory requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.0 functional block descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 task manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 protocol engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 packet transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 packet receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4.1 packet classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.2 classifier operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 ethernet mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 memory management unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.8 jtag interface and board level test features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.0 external interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 packet interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 system function interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5 test facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5.1 administration and control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5.2 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6 miscellaneous inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.7 power and ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.8 internal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.0 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 jtag interface and board level test features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2 external component requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3 miscellaneous features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.0 memory map and register definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.0 test modes operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.1 system normal mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1.2 system tri-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 test mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.3 system normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 system tri-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.0 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 absolute maximum ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4 input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.5 output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 zl50130 data sheet table of contents 4 zarlink semiconductor inc. 9.0 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1 packet interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1.1 mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.1.2 mii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1.3 management interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 external memory interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.3 cpu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.4 system function port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.5 jtag interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.0 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.0 design and layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 high speed clock & data interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.1 external memory interface - spec ial considerations during layout. . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.2 mac interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1.3 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2 cpu ta output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.0 physical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.0 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.1 external standards/specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.2 zarlink zl50130 product related documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.0 related products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.0 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 zl50130 data sheet list of figures 5 zarlink semiconductor inc. figure 1 - high level overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - provider edge inter-working function using the zl50130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3 - zl50130 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4 - zl50130 data flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5 - zl50130 package view and ball positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6 - task manager routing concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7 - mii transmit timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 8 - mii receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 9 - management interface timing for ethernet port - read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 10 - management interface timing for ethernet port - wr ite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 11 - external ram read and write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 12 - cpu read - mpc8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 13 - cpu write - mpc8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 14 - cpu dma read - mpc8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 15 - cpu dma write - mpc8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 16 - jtag signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 17 - jtag clock and reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 18 - powering up the zl50130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 19 - cpu_ta board circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 zl50130 data sheet list of tables 6 zarlink semiconductor inc. table 1 - dma maximum bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2 - mii management interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 3 - mii port 0 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4 - mii port 1 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5 - mii port 2 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6 - mii port 3 interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7 - external memory interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8 - cpu interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9 - system function interface package ball definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 10 - administration/control interface package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 11 - jtag interface package ball definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 12 - miscellaneous inputs package ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13 - power and ground package ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 14 - no connection ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15 - test mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16 - input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 17 - output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18 - mii transmit timing - 100 mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19 - mii receive timing - 100 mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20 - mac management timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 21 - external memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 22 - cpu timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23 - system clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 24 - jtag interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 zl50130 data sheet 7 zarlink semiconductor inc. 1.0 changes summary the following table captures the changes from the september 2004 issue. 2.0 introduction 2.1 overview the zl50130 provides the data-plane proc essing to enable layer 2 ethernet service to be extended over a packet switched network, such as an ip or mpls system. the device encapsulates the ethernet frames into ip or mpls packets, and forwards them into the packet network fo r re-construction at the far end. this has a number of applications, including layer 2 vp ns (virtual private networks). figure 3 - zl50130 operation the zl50130 is capable of wire speed processing and forwarding of packets, and includes support for the ?martini-style? layer 2 pseudo-wire protocols currently in development by the ietf?s pwe3 (pseudo-wire edge-to-edge emulation) working gr oup (draft-ietf-pwe3-ethernet-encap). page item change 10, 11 figure 5 and ball signal assignment table corrected mx_linkup_led pin assigment. 41 8.0 dc characteristics table and output levels table added electrical characterist ics to differentiate between 3.3 v and 5 v tolerant pins. 38 section 4.8 added internal connection (ic) table. 10 figure 5 changed pull_hi and pull_lo pins to icc_vdd_io and ic_gnd. transparent data flow between customer lans (layer 2 vpn service) service provider?s packet switched network ethernet service zl50130 ethernet pseudo-wire device interworking function zl50130 ethernet pseudo-wire device interworking function ethernet service customer lan customer lan zl50130 data sheet 8 zarlink semiconductor inc. 2.2 basic operation a diagram of the zl50130 device is given in figure 4, which shows the major data flows between functional components. figure 4 - zl50130 data flows 2.2.1 psn-bound flow the ethernet switch device aggregates ethernet frames received from each customer into a single ethernet connection. packets are forwarded on this connection to the zl50130, and received by its customer-facing mac interface. valid packets are passed to the pa cket classifier to determine the destination. the protocol engine handles the data- plane requirements of the main higher level protocols (layers 4 and 5) used in typical applications of the zl50130. these include the ethernet pseudo-wire control word (basically a 16-bit sequence number), l2tpv3 connection id, l2tp version 2 and udp. the protocol engine can add a header to the datagram containing up to 24 bytes. this header is largel y static information, and is programmed directly to the cpu. the header may contain a number of dynamic fiel ds, including a length field, checksum, sequence number and a timestamp. the location, and in some cases, the le ngth of these fields is also programmable, allowing the various protocols to be placed at variable locations within the header. packets ready for transmission are queued to the switch fabr ic interface by the packet transmit block. four classes of service are provided, allowing some packet streams to be prioritized ov er others. on trans mission, the packet transmit block appends a programmable header, which has been set up in advance by the control processor. typically this contains the data-link and network layer h eaders (layers 2 and 3), such as ethernet ip, or the mpls tunnel and the vc labels. finally, pack ets are sent out to the packet sw itched network by the psn-facing mac. provider edge interworking function ethernet switch e.g. mvtx2604 mvtx2804 aggregation and adaptation functions phy phy phy phy phy phy phy phy phy customer end services psn bound flow ce bound flow zl50130 ethernet pseudo-wire device packet receive/classifier packet transmit - add layer 2/3 headers task manager memory management / on-chip packet memory host processor interface with dma support protocol engine mac mac packet switch network zl50130 data sheet 9 zarlink semiconductor inc. 2.2.2 ce-bound flow the flow in the reverse direction is essentially similar to the psn-bound flow . packets from the psn are received by its psn-facing mac interface. valid packets are passed to the packet classifier to determine the destination. once this has been determined, the packets are passed to the packet transmit block for forwarding onto the customer. this time, the packet transmit block strips the tunnel header appended on origi nal transmission into the psn. the packets are then queued for transmission by the customer-facing mac. 2.2.3 host packet generation the control processor can generate packets directly, allowi ng it to use the network for out-of-band communications. this can be used for out-of-band trans mission of control data or network setup information, e.g., routing information. the host interface can also be used by a lo cal resource for network transmission of processed data. the device supports dma transfers of packets to and from the cpu memory, using the host?s own dma controller. 2.2.4 external memory requirement the zl50130 includes a la rge amount of on- chip memory, such that for most applications, exter nal memory will not be required. however, for some applications there ma y be a requirement for external memory. therefore, the device allows the external connection of up to 8 mbytes of synchronous zbt sram. zl50130 data sheet 10 zarlink semiconductor inc. zl50130 package view from top side. note that ball a1 is non-chamfered corner. figure 5 - zl50130 package view and ball positions a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af gnd n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd 1 2 3 4 5 6 7 8 91011121314151617181920212223242526 n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c ram_d ata[3] ram_d ata[1] n/c ram_d ata[0] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c ram_d ata[10] ram_d ata[9] ram_d ata[5] ram_d ata[4] ram_d ata[2] n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c gnd n/c n/c n/c n/c ram_d ata[15] ram_d ata[13] ram_d ata[12] ram_d ata[6] ram_d ata[7] gnd vdd_c ore n/c n/c n/c n/c vdd_c ore n/c n/c n/c n/c n/c n/c vdd_c ore gnd n/c n/c n/c n/c m1_lin kup_le ram_d ata[21] ram_d ata[18] ram_d ata[16] ram_d ata[14] ram_d ata[11] ram_d ata[8] n/c n/c m2_lin kup_le m3_lin kup_le n/c m_mdio ram_d ata[25] ram_d ata[24] ram_d ata[23] ram_d ata[19] ram_d ata[17] vdd_c ore vdd_c ore n/c m_mdc m3_crs m3_txc lk m3_rxe r ram_d ata[29] ram_d ata[28] ram_d ata[27] ram_d ata[26] ram_d ata[22] ram_d ata[20] vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io m3_rxd v m3_rxd [3] m3_rxd [2] m3_rxd [1] m3_rxd [0] m3_col ram_pa rity[1] ram_pa rity[0] ram_d ata[31] ram_d ata[30] gnd vdd_c ore vdd_io vdd_c ore gnd m3_txd [3] m3_txe n m3_txe r m3_rxc lk ram_pa rity[7] ram_pa rity[6] ram_pa rity[5] ram_pa rity[4] ram_pa rity[3] ram_pa rity[2] vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_rxe r m1_txc lk m1_crs m3_txd [0] m3_txd [1] m3_txd [2] ram_a ddr[5] ram_a ddr[4] ram_a ddr[2] ram_a ddr[3] ram_a ddr[0] ram_a ddr[1] vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_c ore m1_ref clk m1_rxc lk n/c n/c m1_rxd v gnd ram_a ddr[6] ram_a ddr[7] ram_a ddr[8] gnd vdd_c ore vdd_io gnd gnd gnd gnd gnd gnd vdd_io n/c gnd m1_txe r m1_rxd [2] m1_rxd [3] gnd ram_a ddr[9] ram_a ddr[10] ram_a ddr[11] ram_a ddr[13] ram_a ddr[16] gnd vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd [2] n/c m1_txe n gnd n/c n/c ram_a ddr[12] ram_a ddr[14] ram_a ddr[15] ram_a ddr[19] ic_gnd ic vdd_io gnd gnd gnd gnd gnd gnd vdd_io m1_txd [0] m1_txd [3] n/c n/c m1_col m1_rxd [1] ram_a ddr[17] ram_a ddr[18] ram_b w_b ic_gnd gnd a1vdd vdd_io gnd gnd gnd gnd gnd gnd vdd_io vdd_c ore m1_txd [1] n/c gnd n/c m1_rxd [0] n/c ram_b w_a ram_b w_c ram_r w syste m_deb syste m_clk vdd_io vdd_io n/c m0_rxd [2] n/c m0_txc lk m0_crs n/c n/c ram_b w_d ram_b w_f syste m_rst gpio[2] vdd_c ore vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io vdd_io n/c m0_txe r m0_txe n n/c m0_rxd v m0_rxe r ram_b w_e ram_b w_g gpio[0] gpio[3] gpio[9] ram_d ata[33] m0_txd [2] n/c n/c n/c n/c m0_rxd [3] ram_b w_h gpio[4] gpio[6] gpio[10 ] ram_d ata[32] vdd_c ore vdd_c ore m0_txd [1] n/c n/c m0_col m0_rxd [1] gpio[1] gpio[7] gpio[8] gpio[15 ] ram_d ata[39] gnd ram_d ata[45] ram_d ata[52] vdd_c ore jtag_t ms cpu_ad dr[2] cpu_ad dr[12] vdd_c ore vdd_c ore cpu_da ta[8] cpu_da ta[15] cpu_da ta[23] vdd_c ore m2_rxc lk m2_rxd v gnd m0_txd [0] m0_txd [3] m0_ref clk n/c m0_rxd [0] gpio[5] gpio[11 ] gpio[14 ] ram_d ata[38] ram_d ata[43] ram_d ata[44] ram_d ata[51] ram_d ata[60] test_m ode[1] gnd cpu_ad dr[6] cpu_ad dr[14] cpu_ad dr[23] cpu_ta cpu_da ta[1] cpu_da ta[7] cpu_da ta[12] cpu_da ta[22] cpu_da ta[30] m2_txe r m2_rxd [1] m0_rxc lk m0_lin kup_le m2_act ive_le m1_act ive_le m3_act ive_le gpio[12 ] gpio[13 ] ram_d ata[37] ram_d ata[42] ram_d ata[46] ram_d ata[49] ram_d ata[59] test_m ode[0] jtag_t do cpu_ad dr[4] cpu_ad dr[9] cpu_ad dr[16] cpu_ad dr[22] cpu_cl k cpu_d req0 ic cpu_da ta[10] cpu_da ta[16] cpu_da ta[21] cpu_da ta[27] m2_txd [1] m2_txe n m2_rxd [2] m2_rxe r m2_crs m0_act ive_le ram_d ata[34] ram_d ata[36] ram_d ata[41] ram_d ata[47] ram_d ata[53] ram_d ata[58] ram_d ata[63] jtag_t ck ic_gnd cpu_ad dr[7] cpu_ad dr[11] cpu_ad dr[17] cpu_ad dr[21] cpu_w e cpu_sd ack2 cpu_ir eq1 cpu_da ta[3] cpu_da ta [6] cpu_da ta[14] cpu_da ta[20] cpu_da ta[24] cpu_da ta[29] m2_txd [2] m2_rxd [0] m2_rxd [3] m2_txc lk ram_d ata[35] ram_d ata[40] ram_d ata[48] ram_d ata[54] ram_d ata[57] ram_d ata[62] jtag_t rst ic_gnd cpu_ad dr[3] cpu_ad dr[8] cpu_ad dr[13] cpu_ad dr[18] cpu_ad dr[20] cpu_o e cpu_ts _ale cpu_d req1 ic cpu_da ta [4] cpu_da ta[9] cpu_da ta[13] cpu_da ta[18] cpu_da ta[25] cpu_da ta[28] m2_txd [0] m2_txd [3] m2_col gnd ram_d ata[50] ram_d ata[55] ram_d ata[56] ram_d ata[61] test_m ode[2] jtag_t di ic_gnd cpu_ad dr[5] cpu_ad dr[10] cpu_ad dr[15] cpu_ad dr[19] gnd cpu_cs cpu_sd ack1 ic_vdd _io cpu_ir eq0 cpu_da ta [0] cpu_da ta[5] cpu_da ta [2] cpu_da ta[11] cpu_da ta[17] cpu_da ta[19] cpu_da ta[26] cpu_da ta[31] gnd 1 2 3 4 5 6 7 8 91011121314151617181920212223242526 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af vdd_c ore vdd_io zl50130 data sheet 11 zarlink semiconductor inc. ball signal assignment ball number signal name a1 gnd a2 n/c a3 n/c a4 n/c a5 n/c a6 n/c a7 n/c a8 n/c a9 n/c a10 n/c a11 n/c a12 n/c a13 gnd a14 n/c a15 n/c a16 n/c a17 n/c a18 n/c a19 n/c a20 n/c a21 n/c a22 n/c a23 n/c a24 n/c a25 n/c a26 gnd b1 n/c b2 n/c b3 n/c b4 n/c b5 n/c b6 n/c b7 n/c b8 n/c b9 n/c b10 n/c b11 n/c b12 n/c b13 n/c b14 n/c b15 n/c b16 n/c b17 n/c b18 n/c b19 n/c b20 n/c b21 n/c b22 n/c b23 n/c b24 n/c b25 n/c b26 n/c c1 n/c c2 n/c c3 n/c c4 n/c c5 n/c c6 n/c c7 n/c c8 n/c c9 n/c c10 n/c c11 n/c c12 n/c c13 n/c c14 n/c c15 n/c ball number signal name c16 n/c c17 n/c c18 n/c c19 n/c c20 n/c c21 n/c c22 n/c c23 n/c c24 n/c c25 n/c c26 n/c d1 ram_data[3] d2 ram_data[1] d3 n/c d4 ram_data[0] d5 n/c d6 n/c d7 n/c d8 n/c d9 n/c d10 n/c d11 n/c d12 n/c d13 n/c d14 n/c d15 n/c d16 n/c d17 n/c d18 n/c d19 n/c d20 n/c d21 n/c d22 n/c d23 n/c ball number signal name zl50130 data sheet 12 zarlink semiconductor inc. d24 n/c d25 n/c d26 n/c e1 ram_data[10] e2 ram_data[9] e3 ram_data[5] e4 ram_data[4] e5 ram_data[2] e6 n/c e7 n/c e8 n/c e9 n/c e10 n/c e11 n/c e12 n/c e13 n/c e14 n/c e15 n/c e16 n/c e17 n/c e18 n/c e19 n/c e20 n/c e21 n/c e22 gnd e23 n/c e24 n/c e25 n/c e26 n/c f1 ram_data[15] f2 ram_data[13] f3 ram_data[12] f4 ram_data[6] f5 ram_data[7] ball number signal name f6 gnd f7 vdd_core f8 n/c f9 n/c f10 n/c f11 n/c f12 vdd_core f13 n/c f14 n/c f15 vdd_core f16 n/c f17 n/c f18 n/c f19 n/c f20 vdd_core f21 gnd f22 n/c f23 n/c f24 n/c f25 n/c f26 m1_linkup_led g1 ram_data[21] g2 ram_data[18] g3 ram_data[16] g4 ram_data[14] g5 ram_data[11] g6 ram_data[8] g21 n/c g22 n/c g23 m2_linkup_led g24 m3_linkup_led g25 n/c g26 m_mdio h1 ram_data[25] ball number signal name h2 ram_data[24] h3 ram_data[23] h4 ram_data[19] h5 ram_data[17] h6 vdd_core h21 vdd_core h22 n/c h23 m_mdc h24 m3_crs h25 m3_txclk h26 m3_rxer j1 ram_data[29] j2 ram_data[28] j3 ram_data[27] j4 ram_data[26] j5 ram_data[22] j6 ram_data[20] j9 vdd_io j10 vdd_io j11 vdd_io j12 vdd_io j13 vdd_io j14 vdd_io j15 vdd_io j16 vdd_io j17 vdd_io j18 vdd_io j21 m3_rxdv j22 m3_rxd[3] j23 m3_rxd[2] j24 m3_rxd[1] j25 m3_rxd[0] j26 m3_col k1 ram_parity[1] ball number signal name zl50130 data sheet 13 zarlink semiconductor inc. k2 ram_parity[0] k3 ram_data[31] k4 ram_data[30] k5 gnd k6 vdd_core k9 vdd_io k18 vdd_io k21 vdd_core k22 gnd k23 m3_txd[3] k24 m3_txen k25 m3_txer k26 m3_rxclk l1 ram_parity[7] l2 ram_parity[6] l3 ram_parity[5] l4 ram_parity[4] l5 ram_parity[3] l6 ram_parity[2] l9 vdd_io l11 gnd l12 gnd l13 gnd l14 gnd l15 gnd l16 gnd l18 vdd_io l21 m1_rxer l22 m1_txclk l23 m1_crs l24 m3_txd[0] l25 m3_txd[1] l26 m3_txd[2] m1 ram_addr[5] ball number signal name m2 ram_addr[4] m3 ram_addr[2] m4 ram_addr[3] m5 ram_addr[0] m6 ram_addr[1] m9 vdd_io m11 gnd m12 gnd m13 gnd m14 gnd m15 gnd m16 gnd m18 vdd_io m21 vdd_core m22 m1_refclk m23 m1_rxclk m24 n/c m25 n/c m26 m1_rxdv n1 gnd n2 ram_addr[6] n3 ram_addr[7] n4 ram_addr[8] n5 gnd n6 vdd_core n9 vdd_io n11 gnd n12 gnd n13 gnd n14 gnd n15 gnd n16 gnd n18 vdd_io n21 n/c ball number signal name n22 gnd n23 m1_txer n24 m1_rxd[2] n25 m1_rxd[3] n26 gnd p1 ram_addr[9] p2 ram_addr[10] p3 ram_addr[11] p4 ram_addr[13] p5 ram_addr[16] p6 gnd p9 vdd_io p11 gnd p12 gnd p13 gnd p14 gnd p15 gnd p16 gnd p18 vdd_io p21 m1_txd[2] p22 n/c p23 m1_txen p24 gnd p25 n/c p26 n/c r1 ram_addr[12] r2 ram_addr[14] r3 ram_addr[15] r4 ram_addr[19] r5 ic_gnd r6 ic r9 vdd_io r11 gnd r12 gnd ball number signal name zl50130 data sheet 14 zarlink semiconductor inc. r13 gnd r14 gnd r15 gnd r16 gnd r18 vdd_io r21 m1_txd[0] r22 m1_txd[3] r23 n/c r24 n/c r25 m1_col r26 m1_rxd[1] t1 ram_addr[17] t2 ram_addr[18] t3 ram_bw_b t4 ic_gnd t5 gnd t6 a1vdd t9 vdd_io t11 gnd t12 gnd t13 gnd t14 gnd t15 gnd t16 gnd t18 vdd_io t21 vdd_core t22 m1_txd[1] t23 n/c t24 gnd t25 n/c t26 m1_rxd[0] u1 n/c u2 ram_bw_a u3 ram_bw_c ball number signal name u4 ram_rw u5 system_debug u6 system_clk u9 vdd_io u18 vdd_io u21 n/c u22 m0_rxd[2] u23 n/c u24 m0_txclk u25 m0_crs u26 n/c v1 n/c v2 ram_bw_d v3 ram_bw_f v4 system_rst v5 gpio[2] v6 vdd_core v9 vdd_io v10 vdd_io v11 vdd_io v12 vdd_io v13 vdd_io v14 vdd_io v15 vdd_io v16 vdd_io v17 vdd_io v18 vdd_io v21 n/c v22 m0_txer v23 m0_txen v24 n/c v25 m0_rxdv v26 m0_rxer w1 ram_bw_e ball number signal name w2 ram_bw_g w3 gpio[0] w4 gpio[3] w5 gpio[9] w6 ram_data[33] w21 m0_txd[2] w22 n/c w23 n/c w24 n/c w25 n/c w26 m0_rxd[3] y1 ram_bw_h y2 gpio[4] y3 gpio[6] y4 gpio[10] y5 ram_data[32] y6 vdd_core y21 vdd_core y22 m0_txd[1] y23 n/c y24 n/c y25 m0_col y26 m0_rxd[1] aa1 gpio[1] aa2 gpio[7] aa3 gpio[8] aa4 gpio[15] aa5 ram_data[39] aa6 gnd aa7 ram_data[45] aa8 ram_data[52] aa9 vdd_core aa10 jtag_tms aa11 cpu_addr[2] ball number signal name zl50130 data sheet 15 zarlink semiconductor inc. aa12 cpu_addr[12] aa13 vdd_core aa14 vdd_core aa15 cpu_data[8] aa16 cpu_data[15] aa17 cpu_data[23] aa18 vdd_core aa19 m2_rxclk aa20 m2_rxdv aa21 gnd aa22 m0_txd[0] aa23 m0_txd[3] aa24 m0_refclk aa25 n/c aa26 m0_rxd[0] ab1 gpio[5] ab2 gpio[11] ab3 gpio[14] ab4 ram_data[38] ab5 ram_data[43] ab6 ram_data[44] ab7 ram_data[51] ab8 ram_data[60] ab9 test_mode[1] ab10 gnd ab11 cpu_addr[6] ab12 cpu_addr[14] ab13 cpu_addr[23] ab14 cpu_ta ab15 cpu_data[1] ab16 cpu_data[7] ab17 cpu_data[12] ab18 cpu_data[22] ab19 cpu_data[30] ball number signal name ab20 m2_txer ab21 m2_rxd[1] ab22 m0_rxclk ab23 m0_linkup_led ab24 m2_active_led ab25 m1_active_led ab26 m3_active_led ac1 gpio[12] ac2 gpio[13] ac3 ram_data[37] ac4 ram_data[42] ac5 ram_data[46] ac6 ram_data[49] ac7 ram_data[59] ac8 test_mode[0] ac9 jtag_tdo ac10 cpu_addr[4] ac11 cpu_addr[9] ac12 cpu_addr[16] ac13 cpu_addr[22] ac14 cpu_clk ac15 cpu_dreq0 ac16 ic ac17 cpu_data[10] ac18 cpu_data[16] ac19 cpu_data[21] ac20 cpu_data[27] ac21 m2_txd[1] ac22 m2_txen ac23 m2_rxd[2] ac24 m2_rxer ac25 m2_crs ac26 m0_active_led ad1 ram_data[34] ball number signal name ad2 ram_data[36] ad3 ram_data[41] ad4 ram_data[47] ad5 ram_data[53] ad6 ram_data[58] ad7 ram_data[63] ad8 jtag_tck ad9 ic_gnd ad10 cpu_addr[7] ad11 cpu_addr[11] ad12 cpu_addr[17] ad13 cpu_addr[21] ad14 cpu_we ad15 cpu_sdack2 ad16 cpu_ireq1 ad17 cpu_data[3] ad18 cpu_data[6] ad19 cpu_data[14] ad20 cpu_data[20] ad21 cpu_data[24] ad22 cpu_data[29] ad23 m2_txd[2] ad24 m2_rxd[0] ad25 m2_rxd[3] ad26 m2_txclk ae1 ram_data[35] ae2 ram_data[40] ae3 ram_data[48] ae4 ram_data[54] ae5 ram_data[57] ae6 ram_data[62] ae7 jtag_trst ae8 n/c ae9 cpu_addr[3] ball number signal name zl50130 data sheet 16 zarlink semiconductor inc. n/c - no connect pins, these unused pins must be left open circuit. ic - internally connected. must be left open circuit. ic_gnd - internally connected. tie to ground. ic_vdd_io - internally connected. tie to vdd_io. ae10 cpu_addr[8] ae11 cpu_addr[13] ae12 cpu_addr[18] ae13 cpu_addr[20] ae14 cpu_oe ae15 cpu_ts_ale ae16 cpu_dreq1 ae17 ic ae18 cpu_data[4] ae19 cpu_data[9] ae20 cpu_data[13] ae21 cpu_data[18] ae22 cpu_data[25] ae23 cpu_data[28] ae24 m2_txd[0] ae25 m2_txd[3] ae26 m2_col af1 gnd af2 ram_data[50] af3 ram_data[55] af4 ram_data[56] af5 ram_data[61] af6 test_mode[2] af7 jtag_tdi af8 ic_gnd af9 cpu_addr[5] af10 cpu_addr[10] af11 cpu_addr[15] af12 cpu_addr[19] af13 gnd af14 cpu_cs af15 cpu_sdack1 af16 ic_vdd_io af17 cpu_ireq0 ball number signal name af18 cpu_data[0] af19 cpu_data[5] af20 cpu_data[2] af21 cpu_data[11] af22 cpu_data[17] af23 cpu_data[19] af24 cpu_data[26] af25 cpu_data[31] af26 gnd ball number signal name zl50130 data sheet 17 zarlink semiconductor inc. 3.0 functional block descriptions 3.1 task manager conceptually, the task manager performs the function of a r outer in the centre of the ch ip, directing packets to the appropriate processing blocks. the architecture is based on the task-oriented approach derived from computer science, in which each functional block is considered a se rvice provider or ?subroutine". as a packet is processed in the chip, it receives a specific servic e from a block, returns the flow of c ontrol to the task manager and is then forwarded to the next block for service. the process is ca rried on until it reaches the egress port, as shown in figure 6. the solid arrows illustrate the actual flow of control, while the dotted lines represent the equivalent point-to-point path. figure 6 - task manager routing concept the main function of the task manager is to dispatch task messages to the task blocks. each task block interfaces only with the task manager, not with other task blocks. th e task messages passed between blocks contain pointers to the relevant data, instructions as to what to do with the data and ancillary information about the packet. effectively this means the flow of dat a through the device can be programmed by setting the task message contents appropriately. features include: ? flexible routing of packets through the device ? common interface to all functional blocks ? communication of key parameters between blocks 3.2 protocol engine the protocol engine handles the data-p lane requirements of the upper level pr otocols at layers 4 and 5. it has been designed to handle the requirements of the specific pr otocols expected to be used in typical applications: udp, l2tp versions 2 and 3, and ethernet pseudo-wire. howe ver, it is not exclusively limited to these protocols, since it works by providing a number of dynamic fields that can be updated as required . therefore other protocol headers containing the same types of dy namic fields can also be constructed. the protocol engine can add a header to the datagram c ontaining up to 24 bytes. this header is largely static information and is programmed directly by the cpu. this header may contain a number of dynamic fields, including a length field, checksum, sequence number and a timestamp. the location, and in some cases the length of these fields is also programmable, allowing the various protocols to be placed at variable locations within the header. task manager task block 1 task block 2 task block 3 task block 4 zl50130 data sheet 18 zarlink semiconductor inc. features include: ? up to 24 bytes of higher layer protocol headers (layers 2 to 5) ? specific support for the following protocols: ? udp (rfc 768) ? l2tp versions 2 and 3 (rfc 2661, draft-ietf-l2tpext-l2tp-base-02) ? ethernet pw (draft-i etf-pwe3-ethernet-encap) ? support for the following dynamic fields: ? 16 bit checksum over header and data ? 16 bit datagram length field ? 8 and 16 bit sequence numbers 3.3 packet transmit the packet transmit block serves two main functions. fi rstly, it directs the packets to the appropriate ethernet mac. four separate queues are directed at each mac, allowi ng different classes of service to be established. for instance, packets from the host can be given lower priority service than normal transmission packets. the queues can be managed either on a strict priority basis, or using weighted fair queuing (wfq). there is also a limit on the maximum number of packets in an individual queue. beyond the limit packets are dropped, avoiding a large build-up in packet delay va riation, and preventi ng the memory becoming full and thereby "crashing" the device. secondly, the packet transmit block adds a header to the pa cket before it is sent out for transmission. typically this contains the data-link and network layer headers (layers 2 and 3), such as ethernet, ip and mpls. while the main contents of this header are static and programmed by the us er in a block of memory reserved for each context, certain fields can be dynamically adjusted by the block. these are the ethernet, ipv4 a nd ipv6 length fields and the ipv4 identification field (effectively a sequence numbe r). once the packet header has been appended, any packets that are still smaller than the minimum et hernet packet size (64 bytes) are padded. features include: ? four separate queues to each ethernet mac, with different classes of service ? queue disciplines on packet interface are: ? weighted fair queuing with programmable weights ? strict priority ? programmable drop threshold when queues get too big ? adds up to 64 bytes of layer 2 and layer 3 headers ? automatically adjusts ethernet length, ip length and ip identification fields ? pads small packets to meet the 64 byte minimum ethernet packet size ? packets can be directed to any of the four ethernet macs 3.4 packet receive the packet receive block handles two main functions: wr iting the packet into memory, and identifying the packet received. packets are written into memory as they ar rive at the device. a small buffer is used to cope with simultaneous requests for memory access. the device is capable of accepting packets on 3 ports in mii mode, either ports 0, 1 and 2, or ports 0, 1 and 3. zl50130 data sheet 19 zarlink semiconductor inc. 3.4.1 packet classification the zl50130 contains an extremely flexible packet classifier, capable of operati ng on layers 2 to 5, and identifying 272 separate flows. for instance, it can identify a separa te data and control flow for each context, and a number of other separate flows for sending to the cpu. in addition, the cl assifier can quickly identif y certain specific types of control traffic intended for the cpu, such as arp, rarp and multicast messages. the classifier is designed to handle all the protocols lik ely to occur in networks using the standards developed by the ietf's pwe3, either alone or in combination. these include ethernet (with vlan and snap), ipv4, ipv6, mpls, udp, l2tp versions 2 and 3, and the ethernet pseudo -wire control word. typical protocol stacks which are expected to be used and can be handled by the zl5 0130 include (but are not limited to) the following: the classifier is also used to detect traffic directed to the host cpu. features include: ? automatic forwarding of the following control traffic types to the cpu: ? 802.1 control packets ? ethernet broadcast packets ?ip multicast packets ? arp packets ? rarp packets ? four separate traffic classes ? traffic class identified on any combinat ion fields within the first 64 bytes ? 272 traffic flows (e.g., 128 data, 128 control, 16 host traffic and loopback) ? flow identification based on up to 96 bits, extracted from any field in the first 96 bytes ? mis-connection check, based on up to 64 bits, extracted from any field in the first 96 bytes ? host traffic can be directed to its queue ? ipv4 checksum verification ? support for ip and udp mibs in combination with the cpu 3.4.2 classi fier operation the classifier works in four steps. firs tly, the classifier checks the packet hea der to see if it is one of a number of fixed traffic types. these include 802. 1 control packets, ethernet broadcast packets, ip multicast packets, arp and rarp packets. these types of packets are auto matically forwarded to the cpu at high priority. next the traffic is sorted into one of f our pre-determined traffic classes. this is done by a comparison across the first 64 bytes of the pack et. this will generally c heck fields such as ethertype and the ip protocol field. in addition, the ethernet and ip destination addr ess fields can be checked, to ensure that the packet is intended for this device. ethernet ethernet ethernet ethernet ipv4 / ipv6 ipv4 / ipv6 mpls (tunnel label) stacked vlan (tunnel tag) l2tpv3 udp mpls (vc label) stacked vlan (vc tag) l2tpv2 ethernet pw ethernet pw ethernet pw ethernet pw zl50130 data sheet 20 zarlink semiconductor inc. once the class has been determined, a template is applied, extracting up to 96 bits from any field in the first 96 bytes. these are used to determine the individual flow. fo r example, this could be used to check the cookie value in the l2tpv3 header. the checksum fields can also be verified now, since the protocol stack in use has been determined. when the flow has been identified, up to 64 further bits may be compared to a pre-programmed value as a mis-connection check. for example, the ssrc field in t he rtp header could be checked, or the cookie value in the l2tpv3 header. it could also be used to check ether net or ip source addresses, to check the packet came from the expected source. these 64 bits may again be extract ed from any field in the first 96 bytes. the use of the mis-connection check helps to protect against denial of service attacks, since the cookie or ssrc values are usually hard to guess. at any stage, a failure to match results in the packet bei ng directed to the cpu queue. this enables the host to view the packet and take appropriate action. 3.5 ethernet mac the zl50130 device contains four separate, ieee standard 802.3 compliant, 100 mbit/s ethernet macs. each mac is connected to a physical layer (phy) device via a media independent interface (mii). the mac is responsible for data encapsulation/decapsula tion. this includes frame alignment and synchronization, and detection of physical medium transmission errors. the mac is capable of both full and half-duplex operation. in half-duplex mode it manages the collision avoidance and conten tion resolution process. in the event of a collision, the mac will back off and attempt to re-send the packet up to 16 times. packets for transmission are forwarded to the mac by the packet formatter block. the mac appends the frame check sequence, and generates the preamble and start of frame delimiter before transmi tting out of the mii port. during packet reception, the mac receive section verifies that the frame check sequence is correct, and that the packet is a valid length. packets with an invali d frame check sequence, and data packets longer than a pre-programmed threshold and s horter than 64 bytes are dropped. for ethernet pseudo-wire operation, t he thresholds on the customer-facing macs are usually set shorter than on the psn-facing mac. this is to av oid creating over-sized packets when the additional tunnel headers are added to the packet. the mac also checks the destination field to determine if the packet is intended for the device. if the packet is accepted, it is forwarded on for packet classification, and to be entered into t he appropriate destination queue. illegal packets, or packets intended fo r a different destinat ion are discarded. the mac also collects statistics on t he different types of packets transmitt ed and received on the ethernet. the statistics collected are sufficient to enable the cpu to support the interfaces sections of some common mibs. features include: ? ieee 802.3 compliant operation at 100 mbit/s ? industry-standard mii interface to the physical layer devices ? full and half-duplex operation ? generates preamble, start-of-frame delimiter and frame check sequence ? collision avoidance and contention resolution in half-duplex mode ? verifies frame check sequence and frame length, discarding frames that contain errors ? statistics collection for common mib support: ? rfc 1213 mib ii ? rfc 1757 remote network monitoring mib (for smiv1) zl50130 data sheet 21 zarlink semiconductor inc. ? rfc 2819 remote network monitoring mib (for smiv2) ? rfc 2863 interfaces group mib 3.6 memory management unit the memory management unit handles all access to the on- and off-chip packet memory, arbitrating between the different modules requiring access. efficient use of memory is maintained by allocating memory in small blocks or ?granules?. the zl50130 includes a la rge amount of on- chip memory, such that for most applications, exter nal memory will not be required. however, for some applications there may be a requirement for external memory. therefore the device allows the connection of up to 8 mbytes of synchronous zbt sram. features include: ? on-chip packet memory for self-contained operation ? up to 8 mbytes of off-chip packet memory ? interfaces to bandwidth efficient zbt sram devices ? operates at 100 mhz ? 64 bit wide data path ? supports one memory bank consisting of up to 2x32 bit devices or 1x64 bit device 3.7 host interface the host interface is directly compatible with the moto rola powerquicc? ii microproce ssor family. it provides the host cpu with read and write access to registers, internal memory blocks, and the main on- and off-chip data memory. the device supports dual address dma transfers of packets to and from the cpu memory, using the host's own dma controller. features include: ? interfaces directly to powerquicc? ii (mpc8260) microprocessors using the gpcm ? 32 bit wide data bus ? allows target access to all on-chip registers and memory, and to external packet memory ? dma support, for transfer of packets to and from the host cpu ? flexible interrupt controller zl50130 data sheet 22 zarlink semiconductor inc. table illustrates the maximum bandwidth s achievable by an external dma master. note 1: maximum bandwidths are the maximum the zl50130 devices can transfer under host control, and assumes only minimal packet processing by the host. note 2: combined figures assume the same amount of data is to be transferred each way. 3.8 jtag interface and board level test features the jtag interface is used to access the boundar y scan logic for board level production testing. 4.0 external interface description the following key applies to all tables: i input o output d internal 100 k ? pull-down resistor present u internal 100 k ? pull-up resistor present t tristate output 4.1 packet interfaces the zl50130 the packet interface is capable of 3 mii interfaces. data for packet switching is based on specification ieee std. 802.3 - 2000. 3 ports can be used as 100 mbit/s mii interfaces, either ports 0, 1 and 2 or ports 0, 1 and 3. note: port 2 and port 3 can not be used to receive data simu ltaneously, they are mutually exclusive. they may both be used for packet transmission if required. all packet interface signals are 5 v tolerant, and all outputs are high impedance while system reset is low. dma path packet size max bandwidth mbps 1 zl50130 to cpu only >1000 bytes 50 zl50130 to cpu only 60 bytes 6.7 cpu to zl50130 only >1000 bytes 60 cpu to zl50130 only 60 bytes 43 combined 2 >1000 bytes 58 (29 each way) combined 2 60 bytes 11 (5.5 each way) table 1 - dma maximum bandwidths zl50130 data sheet 23 zarlink semiconductor inc. signal i/o package balls description m_mdc o h23 mii management data clock. common for all four mii ports. it has a minimum period of 400 ns (maximum freq. 2.5 mhz), and is independent of the txclk and rxclk. m_mdio id/ ot g26 mii management data i/o. common for all four mii ports at up to 2.5 mhz. it is bi-directional between the zl50130 and the ethernet station management entity. data is passed synchronously with respect to m_mdc. table 2 - mii management interface package ball definition mii port 0 signal i/o package balls description m0_linkup_led o ab23 led drive for mac 0 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m0_active_led o ac26 led drive for mac 0 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off m0_refclk i d aa24 note: in mii mode this pin must be driven with the same clock as m0_rxclk. m0_rxclk i u ab22 mii - m0_rxclk. accepts the following frequencies: 25.0 mhz mii 100 mbit/s m0_col i d y25 mii - m0_col. collision detection. this signal is independent of m0_txclk and m0_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. table 3 - mii port 0 interface package ball definition zl50130 data sheet 24 zarlink semiconductor inc. m0_rxd[3:0] i u [3] w26 [2] u22 [1] y26 [0] aa26 receive data. clocked on rising edge of m0_rxclk. m0_rxdv i d v25 mii - m0_rxdv receive data valid. active high. this signal is clocked on the rising edge of m0_rxclk. it is asserted when valid data is on the m0_rxd bus. m0_rxer i d v26 mii - m0_rxer receive error. active high signal indicating an error has been detected. normally valid when m0_rxdv is asserted. can be used in conjunction with m0_rxd when m0_rxdv signal is de-asserted to indicate a false carrier. m0_crs i d u25 mii - m0_crs carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. m0_txclk i u u24 mii transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbit/s m0_txd[3:0] o [3] aa23 [2] w21 [1] y22 [0] aa22 transmit data. clocked on rising edge of m0_txclk (mii). m0_txen o v23 mii - m0_txen transmit enable. asserted when the mac has data to transmit, synchronously to m0_txclk with the first preamble of the packet to be sent. remains asserted until the end of the packet transmission. active high. mii port 0 signal i/o package balls description table 3 - mii port 0 interface package ball definition zl50130 data sheet 25 zarlink semiconductor inc. m0_txer o v22 mii - m0_txer transmit error. transmitted synchronously with respect to m0_txclk, and active high. when asserted (with m0_txen also asserted) the zl50130 will transmit a non-valid symbol, somewhere in the transmitted frame. mii port 1 signal i/o package balls description m1_linkup_led o f26 led drive for mac 1 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m1_active_led o ab25 led drive for mac 1 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off m1_refclk i d m22 note: in mii mode this pin must be driven with the same clock as m1_rxclk. m1_rxclk i u m23 mii - m1_rxclk. accepts the following frequencies: 25.0 mhz mii 100 mbit/s m1_col i d r25 mii - m1_col. collision detection. this signal is independent of m1_txclk and m1_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. m1_rxd[3:0] i u [3] n25 [2] n24 [1] r26 [0] t26 receive data. clocked on rising edge of m1_rxclk (mii). table 4 - mii port 1 interface package ball definition mii port 0 signal i/o package balls description table 3 - mii port 0 interface package ball definition zl50130 data sheet 26 zarlink semiconductor inc. m1_rxdv i d m26 mii - m1_rxdv receive data valid. active high. this signal is clocked on the rising edge of m1_rxclk. it is asserted when valid data is on the m1_rxd bus. m1_rxer i d l21 mii - m1_rxer receive error. active high signal indicating an error has been detected. normally valid when m1_rxdv is asserted. can be used in conjunction with m1_rxd when m1_rxdv signal is de-asserted to indicate a false carrier. m1_crs i d l23 mii - m1_crs carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. m1_txclk i u l22 mii transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbit/s m1_txd[3:0] o [3] r22 [2] p21 [1] t22 [0] r21 transmit data. clocked on rising edge of m1_txclk (mii). m1_txen o p23 mii - m1_txen transmit enable. asserted when the mac has data to transmit, synchronously to m1_txclk with the first pre-amble of the packet to be sent. remains asserted until the end of the packet transmission. active high. mii port 1 signal i/o package balls description table 4 - mii port 1 interface package ball definition zl50130 data sheet 27 zarlink semiconductor inc. m1_txer o n23 mii - m1_txer transmit error. transmitted synchronously with respect to m1_txclk, and active high. when asserted (with m1_txen also asserted) the zl50130 will transmit a non-valid symbol, somewhere in the transmitted frame. mii port 2 note: this port must not be used to receive data at the same time as port 3, they are mutually exclusive. signal i/o package balls description m2_linkup_led o g23 led drive for mac 2 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m2_active_led o ab24 led drive for mac 2 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off m2_rxclk i u aa19 mii receive clock. accepts the following frequencies: 25.0 mhz mii 100 mbit/s m2_col i d ae26 collision detection. this signal is independent of m2_txclk and m2_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. m2_rxd[3:0] i u [3] ad25 [1] ab21 [2] ac23 [0] ad24 receive data. clocked on rising edge of m2_rxclk. m2_rxdv i d aa20 receive data valid. active high. this signal is clocked on the rising edge of m2_rxclk. it is asserted when valid data is on the m2_rxd bus. table 5 - mii port 2 interface package ball definition mii port 1 signal i/o package balls description table 4 - mii port 1 interface package ball definition zl50130 data sheet 28 zarlink semiconductor inc. m2_rxer i d ac24 receive error. active high signal indicating an error has been detected. normally valid when m2_rxdv is asserted. can be used in conjunction with m2_rxd when m2_rxdv signal is de-asserted to indicate a false carrier. m2_crs i d ac25 carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. m2_txclk i u ad26 mii transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbit/s m2_txd[3:0] o [3] ae25 [1] ac21 [2] ad23 [0] ae24 transmit data. clocked on rising edge of m2_txclk m2_txen o ac22 transmit enable. asserted when the mac has data to transmit, synchronously to m2_txclk with the first pre-amble of the packet to be sent. remains asserted until the end of the packet transmission. active high. m2_txer o ab20 transmit error. transmitted synchronously with respect to m2_txclk, and active high. when asserted (with m2_txen also asserted) the zl50130 will transmit a non-valid symbol, somewhere in the transmitted frame. mii port 2 note: this port must not be used to receive data at the same time as port 3, they are mutually exclusive. signal i/o package balls description table 5 - mii port 2 interface package ball definition zl50130 data sheet 29 zarlink semiconductor inc. mii port 3 note: this port must not be used to receive data at the same time as port 2, they are mutually exclusive. signal i/o package balls description m3_linkup_led o g24 led drive for mac 3 to indicate port is linked up. logic 0 output = led on logic 1 output = led off m3_active_led o ab26 led drive for mac 3 to indicate port is transmitting or receiving packet data. logic 0 output = led on logic 1 output = led off m3_rxclk i u k26 mii receive clock. accepts the following frequencies: 25.0 mhz mii 100 mbit/s m3_col i d j26 collision detection. this signal is independent of m3_txclk and m3_rxclk, and is asserted when a collision is detected on an attempted transmission. it is active high, and only specified for half-duplex operation. m3_rxd[3:0] i u [3] j22 [1] j24 [2] j23 [0] j25 receive data. clocked on rising edge of m3_rxclk. m3_rxdv i d j21 receive data valid. active high. this signal is clocked on the rising edge of m3_rxclk. it is asserted when valid data is on the m3_rxd bus. m3_rxer i d h26 receive error. active high signal indicating an error has been detected. normally valid when m3_rxdv is asserted. can be used in conjunction with m3_rxd when m3_rxdv signal is de-asserted to indicate a false carrier. m3_crs i d h24 carrier sense. this asynchronous signal is asserted when either the transmission or reception device is non-idle. it is active high. table 6 - mii port 3 interface package ball definition zl50130 data sheet 30 zarlink semiconductor inc. m3_txclk i u h25 mii only - transmit clock accepts the following frequencies: 25.0 mhz mii 100 mbit/s m3_txd[3:0] o [3] k23 [1] l25 [2] l26 [0] l24 transmit data. clocked on rising edge of m3_txclk m3_txen o k24 transmit enable. asserted when the mac has data to transmit, synchronously to m3_txclk with the first pre-amble of the packet to be sent. remains asserted until the end of the packet transmission. active high. m3_txer o k25 transmit error. transmitted synchronously with respect to m3_txclk, and active high. when asserted (with m3_txen also asserted) the zl50130 will transmit a non-valid symbol, somewhere in the transmitted frame. mii port 3 note: this port must not be used to receive data at the same time as port 2, they are mutually exclusive. signal i/o package balls description table 6 - mii port 3 interface package ball definition zl50130 data sheet 31 zarlink semiconductor inc. 4.2 external memory interface all external memory interface signals are 5 v tolerant. all external memory interface outputs are high impedance while system reset is low. if the external memory interface is unused, all input pins may be left unconnected. active low signals are designated by a # suffix, in acco rdance with the convention used in common memory data sheets. signal i/o package balls description ram_data[63:0] iu/ ot [63] ad7 [31] k3 [62] ae6 [30] k4 [61] af5 [29] j1 [60] ab8 [28] j2 [59] ac7 [27] j3 [58] ad6 [26] j4 [57] ae5 [25] h1 [56] af4 [24] h2 [55] af3 [23] h3 [54] ae4 [22] j5 [53] ad5 [21] g1 [52] aa8 [20] j6 [51] ab7 [19] h4 [50] af2 [18] g2 [49] ac6 [17] h5 [48] ae3 [16] g3 [47] ad4 [15] f1 [46] ac5 [14] g4 [45] aa7 [13] f2 [44] ab6 [12] f3 [43] ab5 [11] g5 [42] ac4 [10] e1 [41] ad3 [9] e2 [40] ae2 [8] g6 [39] aa5 [7] f5 [38] ab4 [6] f4 [37] ac3 [5] e3 [36] ad2 [4] e4 [35 ae1 [3] d1 [34] ad1 [2] e5 [33] w6 [1] d2 [32] y5 [0] d4 buffer memory data. synchronous to rising edge of system_clk. ram_parity[7:0] iu/ ot [7] l1 [3] l5 [6] l2 [2] l6 [5] l3 [1] k1 [4] l4 [0] k2 buffer memory parity. synchronous to rising edge of system_clk. bit [7] is parity for data byte [63:56], bit [0] is parity for data byte [7:0]. table 7 - external memory interface package ball definition zl50130 data sheet 32 zarlink semiconductor inc. ram_addr[19:0] o [19] r4 [9] p1 [18] t2 [8] n4 [17] t1 [7] n3 [16] p5 [6] n2 [15] r3 [5] m1 [14] r2 [4] m2 [13] p4 [3] m4 [12] r1 [2] m3 [11] p3 [1] m6 [10] p2 [0] m5 buffer memory address output. synchronous to rising edge of system_clk. ram_bw_a# o u2 synchronous byte write enable a (active low). must be asserted same clock cycle as ram_addr. enables ram_data[7:0]. ram_bw_b# o t3 synchronous byte write enable b (active low). must be asserted same clock cycle as ram_addr. enables ram_data[15:8]. ram_bw_c# o u3 synchronous byte write enable c (active low). must be asserted same clock cycle as ram_addr. enables ram_data[23:16]. ram_bw_d# o v2 synchronous byte write enable d (active low). must be asserted same clock cycle as ram_addr. enables ram_data[31:24]. ram_bw_e# o w1 synchronous byte write enable e (active low). must be asserted same clock cycle as ram_addr. enables ram_data[39:32]. ram_bw_f# o v3 synchronous byte write enable f (active low). must be asserted same clock cycle as ram_addr. enables ram_data[47:40]. ram_bw_g# o w2 synchronous byte write enable g (active low). must be asserted same clock cycle as ram_addr. enables ram_data[55:48] signal i/o package balls description table 7 - external memory interface package ball definition zl50130 data sheet 33 zarlink semiconductor inc. 4.3 cpu interface all cpu interface signals are 5 v tolerant. all cpu interface outputs are high impedance while system reset is low . ram_bw_h# o y1 synchronous byte write enable h (active low). must be asserted same clock cycle as ram_addr. enables ram_data[63:56]. ram_rw# o u4 read/write enable output read = high write = low signal i/o package balls description cpu_data[31:0] i/ ot [31] af25 [15] aa16 [30] ab19 [14] ad19 [29] ad22 [13] ae20 [28] ae23 [12] ab17 [27] ac20 [11] af21 [26] af24 [10] ac17 [25] ae22 [9] ae19 [24] ad21 [8] aa15 [23] aa17 [7] ab16 [22] ab18 [6] ad18 [21] ac19 [5] af19 [20] ad20 [4] ae18 [19] af23 [3] ad17 [18] ae21 [2] af20 [17] af22 [1] ab15 [16] ac18 [0] af18 cpu data bus. bi-directional data bus, synchronously transmitted with cpu_clk rising edge. note: as with all ports in the zl50130 device, cpu_data[0] is the least significant bit (lsb). cpu_addr[23:2] i [23] ab13 [11] ad11 [22] ac13 [10] af10 [21] ad13 [9] ac11 [20] ae13 [8] ae10 [19] af12 [7] ad10 [18] ae12 [6] ab11 [17] ad12 [5] af9 [16] ac12 [4] ac10 [15] af11 [3] ae9 [14] ab12 [2] aa11 [13] ae11 [12] aa12 cpu address bus. address input from processor to zl50130, synchronously transmitted with cpu_clk rising edge. note: as with all ports in the zl50130 device, cpu_addr[2] is the least significant bit (lsb). table 8 - cpu interface package ball definition signal i/o package balls description table 7 - external memory interface package ball definition zl50130 data sheet 34 zarlink semiconductor inc. cpu_cs i u af14 cpu chip select. synchronous to rising edge of cpu_clk and active low. is asserted with cpu_ts _ale. must be asserted with cpu_oe to asynchronously enable the cpu_data output during a read, including dma read. cpu_we i ad14 cpu write enable. synchronously asserted with respect to cpu_clk rising edge, and active low. used for cpu writes from the processor to registers with in the zl50130. asserted one clock cycle after cpu_ts _ale cpu_oe i ae14 cpu output enable. synchronously asserted with respect to cpu_clk rising edge, and active low. used for cpu reads from the processor to registers with in the zl50130. asserted one clock cycle after cpu_ts _ale. must be asserted with cpu_cs to asynchronously enable the cpu_data output during a read, including dma read. cpu_ts _ale i ae15 synchronous input with rising edge of cpu_clk. latch enable (ale), active high signal. asserted with cpu_cs , for a single clock cycle. cpu_sdack1 i af15 cpu/dma 1 acknowledge input. active low synchronous to cpu_clk rising edge. used to acknowledge request from zl50130 for a dma write transaction. only used for dma transfers, not for normal register access. cpu_sdack2 i ad15 cpu/dma 2 acknowledge input active low synchronous to cpu_clk rising edge. used to acknowledge request from zl50130 for a dma read transaction. only used for dma transfers, not for normal register access. signal i/o package balls description table 8 - cpu interface package ball definition zl50130 data sheet 35 zarlink semiconductor inc. cpu_clk i ac14 cpu powerquicc? ii bus interface clock input. 66 mhz clock, with minimum of 6ns high/low time. used to time all host interface signals into and out of zl50130 device. cpu_ta ot ab14 cpu transfer acknowledge. driven from tri-state condition on the negative clock edge of cpu_clk following the assertion of cpu_cs. active low, asserted from the rising edge of cpu_clk. for a read, asserted when valid data is available at cpu_data. the data is then read by the host on the following rising edge of cpu_clk. for a write, is asserted when the zl50130 is ready to accept data from the host. the data is written on the rising edge of cpu_clk following the assertion. returns to tri-state from the negative clock edge of cpu_clk following the de-assertion of cpu_cs. cpu_dreq0 ot ac15 cpu dma 0 request output active low synchronous to cpu_clk rising edge. asserted by zl50130 to request the host initiates a dma write. only used for dma transfers, not for normal register access. cpu_dreq1 ot ae16 cpu dma 1 request active low synchronous to cpu_clk rising edge. asserted by zl50130 to indicate packet data is ready for transmission to the cpu, and request the host initiates a dma read. only used for dma transfers, not for normal register access. cpu_ireqo o af17 cpu interrupt 0 request (active low) cpu_ireq1 o ad16 cpu interrupt 1 request (active low) signal i/o package balls description table 8 - cpu interface package ball definition zl50130 data sheet 36 zarlink semiconductor inc. 4.4 system function interface all system function interface signals are 5 v tolerant. the core of the chip will be held in reset for 16 383 system_clk cycles after system_rst has gone high to allow the pll?s to lock. 4.5 test facilities 4.5.1 administration and control interface all administration and control interface signals are 5 v tolerant. signal i/o package balls description system_clk i u6 system cloc k input. the system clock frequency is 100 mhz. the frequency must be accurate to within 32 ppm in synchronous mode. system_rst i v4 system reset input. active low. the system reset is asynchronous, and causes all registers within the zl50130 to be reset to their default state. system_debug i u5 system debug enable. this is an asynchronous signal that, when de-asserted, prevents the software assertion of the debug-freeze command, regardless of the internal state of registers, or any error conditions. active high. table 9 - system function interface package ball definition signal i/o package balls description gpio[15:0] id/ ot [15] aa4 [7] aa2 [14] ab3 [6] y3 [13] ac2 [5] ab1 [12] ac1 [4] y2 [11] ab2 [3] w4 [10] y4 [2] v5 [9] w5 [1] aa1 [8] aa3 [0] w3 general purpose i/o pins. connected to an internal register, so customer can set user-defined parameters. bits [4:0] reserved at startup or reset for memory tdl setup. see the zl50130 programmers model for more details. test_mode[2:0] i d [2] af6 [1] ab9 [0] ac8 test mode input - ensure these pins are tied to ground for normal operation. 000 sys_normal_mode 001-010 reserved 011 sys_tristate_mode 100-111 reserved table 10 - administration/control interface package ball definition zl50130 data sheet 37 zarlink semiconductor inc. 4.5.2 jtag interface all jtag interface signals are 5 v tolerant, and conform to the requirements of ieee1149.1 (2001). 4.6 miscellaneous inputs signal i/o package balls description jtag_trst i u ae7 jtag reset. asynchronous reset. in normal operation this pin should be pulled low. jtag_tck i ad8 jtag clock - maximum frequency is 25 mhz, typically run at 10 mhz. in normal operation this pin should be pulled either high or low. jtag_tms i u aa10 jtag test mode select. synchronous to jtag_tck rising edge. used by the test access port controller to set certain test modes. jtag_tdi i u af7 jtag test data input. synchronous to jtag_tck. jtag_tdo o ac9 jtag test data output. synchronous to jtag_tck. table 11 - jtag interface package ball definition signal package balls description ic_gnd ad9, af8, r5, t4, ae8 internally connected. tie to gnd. ic_vdd_io af16 internally connected. tie to vdd_io. table 12 - miscellaneous inputs package ball definitions zl50130 data sheet 38 zarlink semiconductor inc. 4.7 power and ground connections 4.8 internal connections table 14 - no connection ball definition signal package balls description vdd_io j9 j10 j11 j12 j13 j14 j15 j16 j17 j18 k9 k18 l9 l18 m9 m18 n9 n18 p9 p18 r9 r18 t9 t18 u9 u18 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 3.3 v vdd power supply for io ring gnd a1 a13 a26 e22 f6 f21 k5 k22 l11 l12 l13 l14 l15 l16 m11 m12 m13 m14 m15 m16 n1 n5 n11 n12 n13 n14 n15 n16 n22 n26 p6 p11 p12 p13 p14 p15 p16 p24 r11 r12 r13 r14 r15 r16 t5 t11 t12 t13 t14 t15 t16 t24 aa6 aa21 ab10 af1 af13 af26 0 v ground supply vdd_core f7 f12 f15 f20 h6 h21 k6 k21 m21 n6 t21 v6 y6 y21 aa9 aa13 aa14 aa18 1.8 v vdd power supply for core region a1vdd t6 1.8 v pll power supply table 13 - power and ground package ball definition signal package balls description ic r6, ac16, ae17 internally connected. must leave open circuit. zl50130 data sheet 39 zarlink semiconductor inc. 5.0 miscellaneous 5.1 jtag interface and board level test features. the jtag interface is used to access the boundar y scan logic for board level production testing. 5.2 external component requirements ? direct connection to powerquicc? ii (mpc8260) host processor and associated memory, but can support other processors with appropriate glue logic. ? ethernet phy for each mac port ? optional zbt-sram for extended packet memory buffer depth 5.3 miscellaneous features ? system clock speed of 100 mhz ? host clock speed of up to 66 mhz ? debug option to freeze all internal state machines ? jtag (ieee1149) test access port ? 3.3 v i/o supply rail with 5 v tolerance ? 1.8 v core supply rail 6.0 memory map and register definitions all memory map and register definitions are in cluded in the zl50130 programmers model document. 7.0 test modes operation 7.1 overview the zl50130 supports the following modes of operation. 7.1.1 system normal mode this mode is the device's normal operating mode. boundary scan testing of the peripheral ring is accessible in this mode via the dedicated jtag pins. the jtag interface is compliant with t he ieee std. 1149.1-2001; test access port and boundary scan architecture. each variant has it's own dedicated .bsdl file wh ich fully describes it's boundary scan architecture. 7.1.2 system tri-state mode all output and i/o output driv ers are tri-stated allowing the device to be isolated when testing or debugging the development board. zl50130 data sheet 40 zarlink semiconductor inc. 7.2 test mode control the system test mode is selected using the dedicated de vice input bus test_mode[2:0] as follows in table 15. 7.3 system normal mode selected by test_mode[2:0] = 3'b000. as the test_mode[2:0 ] inputs have internal pull-downs this is the default mode of operation if no external pull-up/downs are connected. the gpio[15:0] bus is captured on the rising edge of the external reset to provide internal bootstrap options. af ter the internal reset has been de-asserted the gpio pins may be configured by the adm modul e as either inputs or outputs. 7.4 system tri-state mode selected by test_mode[2:0] = 3'b011. all devi ce output and i/o output drivers are tri-stated. system test mode test_mode[2:0] sys_normal_mode 3?b000 sys_tri_state_mode 3?b011 table 15 - test mode control zl50130 data sheet 41 zarlink semiconductor inc. 8.0 dc characteristics 8.1 absolute maximum ratings* *exceeding these figures may cause permanent damage. functional operation under these conditions is not guaranteed. voltage measurements are with respect to ground (v ss ) unless otherwise stated. *the core and pll supply voltages must never be allowed to exceed the i/o supply voltage by more than 0.5 v during power-up. fai lure to observe this rule could lead to a high-current latch-up state, po ssibly leading to chip failure, if sufficient cross-supply cur rent is available. to be safe ensure the i/o supply voltage supply always rises earlier than the core and pll supply voltages. 8.2 recommended operating conditions typical figures are at 25 c and are for design aid only, they are not guaranteed and not subject to production testing. voltage measurements are with respect to ground (v ss ) unless otherwise stated parameter symbol min. max. units i/o supply voltage v dd_io -0.5 5.0 v core supply voltage v dd_core -0.5 2.5 v pll supply voltage v dd_pll -0.5 2.5 v input voltage v i -0.5 v dd + 0.5 v input voltage (5 v tolerant inputs) v i_5v -0.5 7.0 v continuous current at digital inputs i in - 10 ma continuous current at digital outputs i o - 15 ma package power dissipation pd - 4 w storage temperature ts -55 +125 c characteristics symbol min. typ. max. units test condition operating temperature t op -40 25 +85 c junction temperature t j -40 - 125 c positive supply voltage, i/o v dd_io 3.0 3.3 3.6 v positive supply voltage, core v dd_core 1.65 1.8 1.95 v positive supply voltage, core v dd_pll 1.65 1.8 1.95 v input voltage low - all inputs v il --0.8v input voltage high v ih 2.0 - v dd_io v input voltage high, 5 v tolerant inputs v ih_5v 2.0 - 5.5 v zl50130 data sheet 42 zarlink semiconductor inc. 8.3 dc characteristics typical characteristics are at 1.8 v core, 3.3 v i/o, 25 c and typical processing. the min and max values are defined over all process conditions, from -40 to 125 c junction temperature, core voltage 1.65 to 1.95 v and i/o voltage 3.0 and 3.6 v unless otherwise stated. 8.4 input levels table 16 - input levels 8.5 output levels table 17 - output levels characteristics symbol min. typ. max. units. test condition input leakage i leip 1 a no pull up/down v dd_io = 3.6 v output (high impedance) leakage i leop 2 a no pull up/down v dd_io = 3.6 v input capacitance c ip 1pf output capacitance c op 4pf pullup current i pu -27 a input at 0 v pullup current, 5 v tolerant inputs i pu_5v -110 a input at 0 v pulldown current i pd 27 a input at v dd_io pulldown current, 5 v tolerant inputs i pd_5v 110 a input at v dd_io core 1.8 v supply current i dd_core 950 ma pll 1.8 v supply current i dd_pll 1.30 ma i/o 3.3 v supply current i dd_io 120 ma characteristics symbol min. typ. max. units test condition input low voltage v il 0.8 v input high voltage v ih 2.0 v positive schmitt threshold v t+ 1.6 v negative schmitt threshold v t- 1.2 v characteristics symbol min. typ. max. units test condition output low voltage v ol 0.4 v i ol = 6 ma. i ol = 12 ma for packet interface (m*) pins and gpio pins. i ol = 24 ma for led pins. output high voltage v oh 2.4 v i oh = 6 ma. i oh = 12 ma for packet interface (m*) pins and gpio pins. i oh = 24 ma for led pins. zl50130 data sheet 43 zarlink semiconductor inc. 9.0 ac characteristics 9.1 packet interface timing data for the mii packet switching is bas ed on specification ieee std. 802.3 - 2000. 9.1.1 mii transmit timing figure 7 - mii transmit timing diagram parameter symbol 100 mbit/s units notes min. typ. max. txclk period t cc -40-ns txclk high time t chi 14 - 26 ns txclk low time t clo 14 - 26 ns txclk rise time t cr --5ns txclk fall time t cf --5ns txclk rise to txd[3:0] active delay (txclk rising edge) t dv 1 - 25 ns load = 25 pf txclk to txen active delay (txclk rising edge) t ev 1 - 25 ns load = 25 pf txclk to txer active delay (txclk rising edge) t er 1 - 25 ns load = 25 pf table 18 - mii transmit timing - 100 mbit/s t dv t ev t ev t er t er t ch t cl t cc txclk txen txd[3:0] txer zl50130 data sheet 44 zarlink semiconductor inc. 9.1.2 mii receive timing figure 8 - mii receive timing diagram parameter symbol 100 mbit/s units notes min. typ. max. rxclk period t cc -40-ns rxclk high wide time t ch 14 20 26 ns rxclk low wide time t cl 14 20 26 ns rxclk rise time t cr --5ns rxclk fall time t cf --5ns rxd[3:0] setup time (rxclk rising edge) t ds 10 - - ns rxd[3:0] hold time (rxclk rising edge) t dh 5- -ns rxdv input setup time (rxclk rising edge) t dvs 10 - - ns rxdv input hold time (rxclk rising edge) t dvh 5- -ns rxer input setup time (rxcl edge) t ers 10 - - ns rxer input hold time (rxclk rising edge) t erh 5- -ns table 19 - mii receive timing - 100 mbit/s t dh t ds t dvh t dvs t erh t ers t chi t clo t cc rxclk rxdv rxd[3:0] rxer zl50130 data sheet 45 zarlink semiconductor inc. 9.1.3 management interface timing the management interface is common for all inputs and consists of a serial data i/o line and a clock line. note 1: refer to clause 22 in ieee802.3 (2000) standard for input/output signal ti ming characteristics note 2: refer to cla use 22c.4 in ieee802.3 (2 000) standard for output load description of mdio figure 9 - management interface timing for ethernet port - read figure 10 - management interface timing for ethernet port - write parameter symbol min. typ. max. units notes m_mdc clock output period t mp 1990 2000 2010 ns note 1 m_mdc high t mhi 900 1000 1100 ns m_mdc low t mlo 900 1000 1100 ns m_mdc rise time tmr - - 5 ns m_mdc fall time t mf --5ns m_mdio setup time (mdc rising edge) t ms 10 - - ns note 1 m_mdio hold time (m_mdc rising edge) t mh 10 - - ns note 1 m_mdio output delay (m_mdc rising edge) t md 1 - 300 ns note 2 table 20 - mac management timing specification t mh t ms t mlo t mhi m_mdc m_mdio t md t mp m_mdc m_mdio zl50130 data sheet 46 zarlink semiconductor inc. 9.2 external memory interface timing the timings for the external memory interface are based on the requirements of a zbt-sram device, with the system clock speed at 100 mhz. note 1: must be capable of driving two separate ram loads simultaneously figure 11 - external ram read and write timing parameter symbol min. typ. max. units notes ram_data[63:0] output valid delay t rdv - - 4 ns load c l = 30 pf ram_rw/ram_addr[19:0] delay t rav - - 4 ns load c l = 30 pf note 1 ram_bw[7:0]# delay t rbw - - 4 ns load c l = 30 pf ram_data[63:0] setup time t rds 2- -ns ram_data[63:0] hold time t rdh 0.5 - - ns ram_parity[7:0] output valid delay t rpv - - 4 ns load c l = 30 pf ram_parity[7:0] setup time t rps 2- -ns ram_parity[7:0] hold time t rps 0.5 - - ns table 21 - external memory timing n phase 1 phase 2 phase 3 phase 4 phase 5 phase 6 phase 7 phase 8 a1 a2 a3 a4 a5 a6 a7 a8 bw1 bw2 bw3 bw4 bw5 bw6 bw7 bw8 d(a1) q(a2) q(a3) d(a4) d(a5) q(a6) p(a1) p(a2) p(a3) p(a4) p(a5) p(a6) t rpv t rpv t rdv t rdv t rbw t rav t rav t rav t rav t rph t rps t rdh t rds t rdh t rds sclk ram_addr[19:0] ram_rw ram_bw[7:0] ram_data[63:0] ram_parity[7:0] a1 - read a2 - write a3 - write a4 - read a5 - read a6 - write a7 - read a8 - write zl50130 data sheet 47 zarlink semiconductor inc. 9.3 cpu interface timing note 1: load = 50 pf maximum note 2: the maximum value of t ctv may cause setup violations if directly connected to the mpc8260. see section 11.2 for details of how to accommodate this during board design parameter symbol min. typ. max. units notes cpu_clk period t cc 15.152 ns cpu_clk high time t cch 6ns cpu_clk low time t ccl 6ns cpu_clk rise time t ccr 4ns cpu_clk fall time t ccf 4ns cpu_addr[23:2] setup time t cas 4ns cpu_addr[23:2] hold time t cah 2ns cpu_data[31:0] setup time t cds 4ns cpu_data[31:0] hold time t cdh 2ns cpu_cs setup time t css 4ns cpu_cs hold time t csh 2ns cpu_we /cpu_oe setup time t ces 5ns cpu_we /cpu_oe hold time t ceh 2ns cpu_ts _ale setup time t cts 4ns cpu_ts _ale hold time t cth 2ns cpu_sdack1 /cpu_sdack2 setup time t cks 2ns cpu_sdack1 /cpu_sdack2 hold time t ckh 2nsnote 1 cpu_ta output valid delay t ctv 2 11.3 ns note 1,2 cpu_dreq0 /cpu_dreq1 output valid delay t cwv 26nsnote 1 cpu_ireq0 /cpu_ireq1 output valid delay t crv 26nsnote 1 cpu_data[31:0] output valid delay t cdv 27nsnote 1 cpu_cs to output data valid t sdv 3.2 10.4 ns cpu_oe to output data valid t odv 3.3 10.4 ns cpu_clk(falling) to cpu_ta valid t otv 9.5 ns table 22 - cpu timing specification zl50130 data sheet 48 zarlink semiconductor inc. the actual point where read/write data is transferred occurs at the positive clock edge following the assertion of cpu_ta , not at the positive clock edge during the assertion of cpu_ta . figure 12 - cpu read - mpc8260 figure 13 - cpu write - mpc8260 t otv t ctv t ctv t otv t sdv t odv t cdv t sdv t odv t cth t cts t ceh t ces t csh t css t cah t cas 0 or more cycles 0 or more cycles t cc note: cpu_data is valid when cpu_ta is asserted. cpu_data will re main valid while both cpu_cs and cpu_oe are asserted. cpu_ta will continue to be driven until cpu_cs is deasserted. cpu_clk cpu_addr[23:2] cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta cpu_cs and cpu_oe must both be asserted to enable the cpu_data output. t otv t ctv t ctv t otv t cdh t cds t cth t cts t ceh t ces t csh t css t cah t cas 0 or more cycles 0 or more cycles t cc 0 or more cycles 0 or more cycles note: following assertion of cpu_ta, cpu_cs may be deasserted. the mpc8260 will continue to assert cpu_cs until cpu_ta has been synchronized internally. cpu_ ta will continue to be driven until cpu_cs is finally deasserted. during continued assertion of cpu_cs, cpu_we and cpu_data may be removed. cpu_clk cpu_addr[23:2] cpu_cs cpu_oe cpu_we cpu_ts_ale cpu_data[31:0] cpu_ta zl50130 data sheet 49 zarlink semiconductor inc. figure 14 - cpu dma read - mpc8260 figure 15 - cpu dma write - mpc8260 t otv t ctv t ctv t otv t sdv t odv t cdv t sdv t odv t cwv t cwv t cth t cts t ceh t ces t csh t css t ckh t cks 0 or more cycles 0 or more cycles t cc note: cpu_sdack2 must be asserted during the cycle shown. it may then be deasserted at any time. cpu_data is valid when cpu_ta is asserted (always timed as shown) . cpu_data will remain valid while cpu_cs and cpu_oe are asserted. cpu_ta will continue to be driven until cpu_cs is deasserted. cpu_cs and cpu_oe must both be asserted to enable cpu_clk cpu_dreq1 cpu_sdack2 cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta the cpu_data output. t otv t ctv t ctv t otv t cwv t cwv t cdh t cds t cth t cts t ceh t ces t csh t css t ckh t cks 0 or more cycles 0 or more cycles t cc note: cpu_sdack1 must be asserted during the cycle shown. it may then be deasserted at any time. following assertion of cpu_ta (always timed as shown), cpu_cs may be deasserted. the mpc8260 will continue to assert cpu_cs until cpu_ta has been synchronized internally. cpu_ta will continue to be driven until cpu_cs is finally deasserted. during continued assertion of cpu_cs , cpu_we and cpu_data may be removed. cpu_clk cpu_dreq0 cpu_sdack1 cpu_cs cpu_oe cpu_we cpu_ts _ale cpu_data[31:0] cpu_ta zl50130 data sheet 50 zarlink semiconductor inc. 9.4 system function port note 1: the system clock frequency stability affects the holdover-operating mode of the dpll. holdover mode is typically used fo r a short duration while network synchronisation is temporarily disrupted. drift on the system clock directly affects the holdover mode accuracy. note that the absolute system clock accuracy does not affect the holdover accuracy, only the change in the system clock (system_clk) accuracy while in holdover. for example, if the syst em clock oscillator has a temperature coefficient of 0.1ppm/oc, a 10oc change in temp erature while the dpll is in will result in a frequency accuracy offset of 1ppm. the intrinsic frequency accuracy of the dpll holdover mode is 0.06 ppm, excluding the system clock drift. note 2: the system clock frequency affects the operation of the dpll in free-run mode. in this mode, the dpll provides timing an d synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e. frequency of clock output equals 8.192 mhz system_c lk accuracy 0.005 ppm). note 3: the absolute system_clk accuracy must be controlled to 30 ppm in synchronous master mode to enable th e internal dpll to function correctly. note 4: in asynchronous mode and in synchronous slav e mode the dpll is not used. theref ore the tole rance on system_clk may be relaxed slightly. parameter symbol min. typ. max. units notes system_clk frequency clk fr - 100 - mhz note 1 and note 2 system_clk accuracy (synchronous master mode) clk acs - - 30 ppm note 3 system_clk accuracy (synchronous slave mode and asynchronous mode) clk aca - - 200 ppm note 4 table 23 - system clock timing zl50130 data sheet 51 zarlink semiconductor inc. 9.5 jtag interface timing note 1: jtag_trst is an asynchronous signal. the setup time is for test purposes only. note 2: non test (other than jtag_tdi and jtag_tms) signal input timing with respect to jtag_clk note 3: non test (other than jtag_tdo) signal output with respect to jtag_clk parameter symbol min. typ. max. units notes jtag_clk period t jcp 40 100 ns jtag_clk clock pulse width t low, t high 20 - - ns jtag_clk rise and fall time t jrf 0-3ns jtag_trst setup time t rstsu 10 - - ns with respect to jtag_clk falling edge. note 1 jtag_trst assert time t rst 10 - - ns input data setup time t jsu 5- -nsnote 2 input data hold time t jh 15 - - ns note 2 jtag_clk to output data valid t jdv 0 - 20 ns note 3 jtag_clk to output data high impedance t jz 0 - 20 ns note 3 jtag_tms, jtag_tdi setup time t tpsu 5- -ns jtag_tms, jtag_tdi hold time t tph 15 - - ns jtag_tdo delay t topdv 0 - 15 ns jtag_tdo delay to high impedance t tpz 0 - 15 ns table 24 - jtag interface timing zl50130 data sheet 52 zarlink semiconductor inc. figure 16 - jtag signal timing figure 17 - jtag clock and reset timing don't care dc hiz hiz t tpz t topdv t tph t tpsu t tph t tpsu t jcp t low t high jtag_tck jtag_tms jtag_tdi jtag_tdo t rstsu t rst t high t low jtag_tck jtag_trst zl50130 data sheet 53 zarlink semiconductor inc. 10.0 power up sequence to power up the zl50130 the following procedure must be used: ? the core supply must never exceed the i/o supply by more than 0.5 v dc . ? both the core supply and the i/o supply must be brought up together ? the system reset and, if used, the jtag reset must remain low until at least 100 s after the 100 mhz system clock has stabilised. note that if jtag reset is not used it must be tied low. this is illustrated in the diagram shown in figure 18. figure 18 - powering up the zl50130 rst sclk v dd i/o supply (3.3 v) core supply (1.8 v) 10ns > 100s <0.5 v dc t t t zl50130 data sheet 54 zarlink semiconductor inc. 11.0 design and layout guidelines this guide will provide information and guidance for pcb layouts when us ing the zl50130. sp ecific areas of guidance are: ? high speed clock and data, outputs and inputs ? cpu_ta output 11.1 high speed clock & data interfaces on the zl50130 series of devices there are three high-sp eed data interfaces that need consideration when laying out a pcb to ensure correct termination of traces and the reduction of crosstalk noise. the interfaces being: ? external memory interface ? mac interfaces ? cpu interface in general the output drivers used in the zl50130 are capabl e of driving modest capaciti ve loads with a reasonably fast edge speed (<2.5 ns). therefore these outputs are not designed to drive multiple loads, connectors, backplanes or cables. it is recommended that the outputs are suitably terminated using a series termination through a resistor as close to the output pin as possible. the purpose of the series termination resist or is to reduce reflections on the line. the value of t he series termination and the length of trace the output can drive will depend on the driver output impedance, th e characteristic impedance of the pcb trace (recommend 50 ohm), the distributed trace capacitance and the load capacitance. as a general rule of thumb, if the trace length is less than 1/6th of the equivalent leng th of the rise and fall times, then a series termination may not be required. the equivalent length of rise time = rise time (ps) / delay (ps/mm) for example: typical fr4 board delay = 6.8 ps/mm typical rise/fall time for a zl50130 output = 2.5 ns critical track length = (1/6) x (2500/6.8) = 61 mm therefore tracks longer than 61 mm will require termination. as a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is crosstalk. if the crosstalk is of sufficiently strong ampl itude, false data can be induced in the trace and therefore it should be minimized in the layout. the voltage that the extern al fields cause is proportional to the strength of the field and the length of the tr ace exposed to the field. therefore to mini mize the effect of crosstalk some basic guidelines should be followed. first, increase separation of sensitive signals, a rough ru le of thumb is that doubling the separation reduces the coupling by a factor of four. alternativ ely, shield the victim traces from the aggressor by either routing on another layer separated by a power plane (in a correctly decouple d design the power planes have the same ac potential) or by placing guard traces between the signals usually held ground potential. 11.1.1 external memory interface - special considerations during layout the timing of address, data and control are all related to the system clock which is also used by the external ssram to clock these signals. therefore the propagation delay of the clock to the zl50130 and the ssram must be matched to within 250 ps, worst case conditions. tr ace lengths of theses sign als must also be minimized (<100 mm) and matched to ensure corre ct operation under all conditions. zl50130 data sheet 55 zarlink semiconductor inc. 11.1.2 mac interface - spec ial considerations during layout the mii interface passes data to and from the zl50130 with their related transmit and rece ive clocks. it is therefore recommended that the trace lengths for transmit related si gnals and their clock and the receive related signals and their clock are kept to the same lengt h. by doing this the skew between indi vidual signals and thei r related clock will be minimized. 11.1.3 summary particular effort should be made to minimize crosstalk from zl50130 outputs and ensuring fast rise time to these inputs. in summary: ? place series termination resistors as close to the pins as possible. ? minimize output capacitance. ? keep common interface traces close to the same length to avoid skew. ? protect input clocks and signals from crosstalk. 11.2 cpu ta output the cpu_ta output signal from the zl50130 is a critical handshake signal to the cpu that ensures the correct completion of a bus transaction between the two devices. as the signal is critic al, it is recommend that the circuit shown in figure 19 is implemented in systems operat ing above 40 mhz bus frequency to ensure robust operation under all conditions. ? the following external logic is required to implement the circuit: ? 74lcx74 dual d-type flip-flop (one section of two) ? 74lcx08 quad and gate (one section of four) ? 74lcx125 quad tri-state buffer (one section of four) ? 4k7 resistor x2 figure 19 - cpu_ta board circuit d q cpu_clk cpu_ta from zl50130 cpu_cs to zl50130 to zl50130 +3v3 +3v3 cpu_ta to cpu r1 r2 4k7 4k7 zl50130 data sheet 56 zarlink semiconductor inc. the function of the circuit is to extend the ta signal, to ensure the cpu corr ectly registers it. resistor r2 must be fitted to ensure correct operati on of the ta input to the processor. it is recommended that the logic is fitted close to the zl50130 and that the clock to the 74lcx74 is derived fr om the same clock source as that input to the zl50130. 12.0 physical specification the zl50130 will be packaged in a pbga device. features: ? body size: 35 mm x 35 mm (typ) ? ball count: 552 ? ball pitch: 1.27 mm (typ) ? ball matrix: 26 x 26 ? ball diameter: 0.75 mm (typ) ? total package thickness: 2.33 mm (typ) zl50130 data sheet 57 zarlink semiconductor inc. 13.0 reference documents 13.1 external standards/specifications ? ieee standard 1149.1-2001; test access port and boundary scan architecture ? ieee standard 802.3-2000; local and metropolitan networks csma/cd access method and physical layer ? mpc8260aec/d revision 0.7; motorola mpc8260 family hardware specification ? rfc 768; udp ? rfc 791; ipv4 ? rfc2460; ipv6 ? rfc 1889; rtp ? rfc 2661; l2tp ? rfc 1213; mib ii ? rfc 1757; remote network monitoring mib (for smiv1) ? rfc 2819; remote network monitoring mib (for smiv2) ? rfc 2863; interfaces group mib ? ietf?s pwe3 draft-ietf-l2tpext-l2tp-base-02 ? optional packet memory device - micron mt55l128l32p1 8 mb zbt-sram 13.2 zarlink zl50130 product related documentation ? zl50130 programmers model ? zl50130 api users guide ? zl50130 product preview 14.0 related products ? mvtx260x 24 port 10/100 mbit/s ethernet switch ? mvtx280x 4/8 port gigabit ethernet switch ? zl50418 ethernet switches zl50130 data sheet 58 zarlink semiconductor inc. 15.0 glossary context a programmed connection representing a unique packet stream. cpu central processing unit dma direct memory access ietf internet engineering task force ip internet protocol (version 4, rfc 791, version 6, rfc 2460) jtag joint test algorithms group (generally used to refer to a standard way of providing a board-level test facility) l2tp layer 2 tunneling protocol (rfc 2661) lan local area network mac media access control mii media independent interface mib management information base mpls multi protocol label switching pll phase locked loop psn packet switched network pwe3 pseudo-wire end-to-end emulation (a working group of the ietf) ssram synchronous static random access memory udp user datagram protocol (rfc 768) vlan virtual local area network wfq weighted fair queuing zbt zero bus turnaround, a type of synchronous sram c zarlink semiconductor 2003 all rights reserved. issue apprd. date acn package code previous package codes 1 213837 12dec02 2 19aug03 www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at |
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